8051 microcontroller interrupts

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When several interrupt sources request interrupts from the CPU at the same time, according to the priority of the real-time events that occur, priority is given to the interrupt request of the most urgent event, so the microcontroller specifies the priority level of each interrupt source.

When the CPU is processing an interrupt request and another interrupt request with a higher priority is generated, the CPU temporarily suspends the previous interrupt processing and then processes the interrupt request with a higher priority. After the processing is completed, the CPU continues to execute. The original interrupt handler, such a process is called interrupt nesting, such an interrupt system is called a multi-level interrupt system.

Since the external asynchronous event interrupts the program being executed by the CPU at random, when the CPU turns to execute the interrupt service routine, in addition to the hardware automatically pushes the power-down address, that is, the value of the 16-bit PC program counter onto the stack, the user has to pay attention. Protects information about working registers, accumulators, flags, etc. This process is often referred to as protecting the scene. In order to restore the contents of the original working register, accumulator, flag, etc. after the completion of the interrupt service routine, this process is said to restore the scene; finally, the interrupt return instruction is executed, the power is automatically turned off to the PC, the main program is returned, and the execution is interrupted. program.

Let's take a look at the 8051 interrupt system structure and interrupt control:

The 8051 microcontroller has five interrupt request sources, four registers for interrupt control, IE.IP.TCON and SCON, which are used to control the type of interrupt, interrupt enable, interrupt start and stop, and priority levels of various interrupt sources.

The five interrupt sources have two priority levels, and each interrupt source can be programmed as a high priority or low priority interrupt to enable nesting of the secondary interrupt service routine. The 8051 interrupt sources include:

INT0, external interrupt source for INT1 pin input

Three internal interrupt sources, the overflow interrupt source of timer T0, the overflow interrupt source of timer T1, and the transmit/receive interrupt source of the serial port. Regarding the internal interrupt source, we will talk about it later. Today we will learn about the external interrupt source.


The two external interrupt sources input from the INT0, INT1 pins and their trigger mode control bits are latched in the lower four bits of the Special Function Register TCON in the following format:



IE1, TCON.3:

External interrupt INT1 request flag bit. When the CPU detects an external interrupt signal appearing on the INT1 pin, IE1 = 1 is set by hardware to request an interrupt. After the CPU executes the interrupt service routine, the IE1 bit is automatically cleared by hardware.

IT1, TCON.2:

External interrupt INT1 request type, trigger mode control bit, set or cleared by software to control the trigger type of external interrupt 1.

   IT1=0, external interrupt 1 is set to level trigger mode. When pin INT1 is input low level, IE1 is set and the interrupt is requested. The CPU samples the input level of INT1 during S5P2 of each machine cycle, and sets IE1 = 1 when sampling low. When using the level trigger mode, the external interrupt source input to pin INT1 must remain active until the program is responded by the CPU. At the same time, the external interrupt source active level must be revoked before the interrupt service routine is executed, otherwise it will be generated and another interrupt.

   IT1=1, external interrupt 1 is set to edge trigger mode, and the CPU samples the level of pin INT1 every machine cycle. If one of the two consecutive samples is sampled to pin INT1 high, then the next cycle samples to pin INT1 low, INE1 is automatically cleared by hardware. Because each machine cycle samples an external interrupt The input level, the high-level and low-level times of the external interrupt source input must be maintained for more than 12 oscillator cycles to ensure that the CPU detects a negative transition signal, that is, a falling edge.


IEO, TCON.1: External Interrupt Request Flag. When IE0 = 1, external interrupt 0 requests an interrupt from the CPU. When the CPU responds to an external interrupt, IE0 is cleared by hardware.

ITO, TCON.0: External Interrupt 0 Trigger Mode Control Bit. IT0=0, external interrupt 0 is set to edge trigger mode. When IT0 = 1, external interrupt 0 is set to the edge level mode. Its function is similar to IT1.


Interrupt Control: In addition to the special function registers TCON and SCON, some bits are related to interrupts. There are also two special function registers, IE and IP, dedicated to interrupt control.

Interrupt allows IE:


In the 8051 MCU, the special function register IE bit interrupt enable register controls whether the CPU allows or disables the interrupt source and whether each interrupt source allows interrupts. Its format is:

EA: Interrupt the total allowed bit. EA=1, the CPU allows interrupts; EA=0, the CPU disables all interrupt requests.

ES: Serial interrupt enable bit. ES=1, serial port interrupt is allowed; ES=0, serial port interrupt is disabled.

EX1: T0 overflow interrupt enable bit. ET0=1, T0 interrupt is allowed; ET0=0, T0 interrupt is disabled.

EX0:: External interrupt enable bit. EX0=1, external interrupt 0 interrupt is enabled; EX0=0, external interrupt 0 interrupt is disabled.

After the 8051 system is reset, all the bits in the IE are cleared to 0, that is, all interrupts are disabled.


Interrupt priority setting register IP. The 8051 microcontroller has two interrupt priority levels, each interrupt source can be programmed as a high priority interrupt or a low priority interrupt, and can achieve two levels of interrupt nesting. A high priority interrupt source can interrupt the low priority interrupt service routine being executed;

A peer or low priority interrupt source cannot interrupt the interrupt routine being executed. To this end, in the 8051 interrupt system, there are two priority status triggers internally, which indicate whether the CPU is executing a high priority or low priority interrupt service routine, thereby shielding all interrupt requests and other levels of the same level. Interrupt source request.

The special function register IP is the interrupt priority register.


The control bits of each interrupt source priority can be set by the user. Its format is as follows


PS: Serial interrupt priority control bit. PS=1, set the serial port as a high priority interrupt; PS=0, which is a low priority.

PT1: T1 interrupt priority control bit. PT1=1, set timer T1 to be a high priority interrupt; PT=0, which is a low priority.

TX1: External interrupt 1 interrupt priority level control bit. PX1=1 sets external interrupt 1 to high priority interrupt; PC1=0, which is low priority.

PT1: T1 interrupt priority control bit. PT1=1, set timer T1 to be a high priority interrupt; PT1=0, which is a low priority.

PT0: T0 interrupt priority control bit. PT1=1, set timer T0 to be a high priority interrupt; PT0=0, which is a low priority.

PX0: External interrupt interrupt priority control bit. PX0=1, set INT1 to high priority. PX0=0, which is low priority.


After the 8051 reset, all five low IP bits are cleared to 0, and all interrupt sources are set to low priority interrupts.

If several interrupt sources of the same priority request an interrupt to the CPU at the same time, which application is serviced depends on the sequence number of the queues that are registered in the CPU. The CPU queries the registration number through the internal hardware, and decides which interrupt request is preferentially responded according to the natural priority. The natural priority is in order from high to low: external interrupt 0, timer 0, external interrupt 1, timer 1, serial interrupt.


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